Michael Yin
About Michael Yin
Michael Yin is a Staff Engineer with extensive experience in microarchitecture and RTL design, currently working at Achronix Semiconductor Corporation in Santa Clara, California. He has held various engineering roles since 1998 and holds a Master's degree in Electrical Engineering from Santa Clara University.
Current Role at Achronix Semiconductor Corporation
Michael Yin serves as a Staff Engineer at Achronix Semiconductor Corporation, a position he has held since 2016. He is based in Santa Clara, California, where he contributes to the company's initiatives in semiconductor technology. His role involves leveraging his expertise in microarchitecture and RTL design to enhance product development and innovation.
Experience at Geo Semiconductor, Inc.
Since 2016, Michael Yin has also worked as a Principal Engineer at Geo Semiconductor, Inc. in San Jose, California. In this capacity, he focuses on advanced semiconductor solutions, utilizing his extensive background in IP design and integration. His experience in the industry spans over eight years at this organization, where he has played a crucial role in various engineering projects.
Previous Positions in the Semiconductor Industry
Prior to his current roles, Michael Yin worked at Prysm Inc. as a Senior FPGA Engineer from 2013 to 2016 in San Francisco, California. He also held engineering positions at Teralogics, LLC from 1998 to 2001 and Synopsys from 2001 to 2004. These experiences provided him with a solid foundation in FPGA design and hardware emulation.
Educational Background in Electrical Engineering
Michael Yin earned his Master of Science degree in Electrical Engineering from Santa Clara University. He also holds a Bachelor of Science degree in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His academic background has equipped him with the technical knowledge necessary for his engineering roles.
Expertise in Semiconductor Design
Michael Yin possesses expertise in microarchitecture, RTL design, synthesis, timing closure, and static timing analysis. He specializes in IP design and integration, and has been involved in several full design cycles, including initial specification and algorithm development. His experience also includes FPGA design for hardware emulation and tapeout.