Mason R.
About Mason R.
Mason R. is an FPGA Engineer II at Astranis, where he oversees the Satellite Software Defined Radio Payload FPGAs. He has a background in computer engineering and has held various roles in academia and industry, including positions at NASA and the University of Florida.
Work at Astranis
Mason R. has been employed at Astranis as an FPGA Engineer II since 2018. In this role, he is responsible for the Satellite Software Defined Radio Payload (DSP) FPGAs. His work involves managing schedules and resources for multiple FPGA projects simultaneously. Prior to his current position, he worked as an FPGA Engineer Contractor and as an FPGA Engineer Intern at Astranis in 2017 and 2018, respectively.
Experience at NASA
Mason R. worked at NASA as a Pathways Co-Op in Photovoltaic and Electrochemical Systems from 2015 to 2016 for five months. This role took place in the Cleveland/Akron, Ohio Area. During his time at NASA, he developed extensive Python APIs and test software to interface with FPGAs, showcasing his technical skills in a high-stakes environment.
Education and Expertise
Mason R. earned a Bachelor of Science in Computer Engineering from the University of Florida, completing his studies from 2014 to 2018. His education provided a strong foundation in engineering principles, which he has applied throughout his career in various roles related to FPGA design and implementation.
Previous Roles and Responsibilities
Before joining Astranis, Mason R. held several positions at the University of Florida, including Research Assistant, Tutor, and Teaching Assistant for Computer Hardware Engineering Courses. He also served as a Thermal Aware Computing Researcher and as an FPGA Image Processing Application Lead at CHREC. In these roles, he mentored interns and contributed to the development of quality RTL code for space applications.
Technical Contributions
Mason R. has made significant technical contributions throughout his career. He successfully brought up 12.5Gbps JESD204B to data converters on custom digital hardware. Additionally, he achieved over 80% utilization at a frequency of 300+ MHz on a Xilinx FPGA, demonstrating his proficiency in high-performance FPGA design.