Zhonghe Song
About Zhonghe Song
20+ years of low-power, low-cost ASIC design experience implementing wireless communication applications Proven track record with many successful full-cycle ASIC developments from concept to production Experience and practical application of general IC design concepts and considerations Experience on CDC(cross clock domain) design Experience on power domain, power gate design. Proficient with RTL (VHDL, Verilog, VerilogAms) coding and simulation Experienced with Synthesis and timing closure using Synopsys, Cadence tool sets Experienced with P&R using Cadence Encounter tools Experienced with Formal verification using Mentor (FormalPro) and Cadence (LEC) tool DFT (Scan, BIST) design and test pattern generation (ATPG) using Mentor and Cadence tool Experienced with ASIC bring up, silicon debugging, IC characterization using a variety of Lab equipment Intensive working experience of mapping DSP function to hardware such as IIR, FIR, Decimation, Interpolation, CIC filter design, error control coding (Viterbi, Turbo), synchronization design (timing recovery, frequency/phase estimation and correction), channel equalization Experienced in multi-million gate FPGA implementation with Xilinx SOC design using ARC, ARM, SPARC embedded processors, and PCIe, AMBA, USB elements Interface design (SPI, MIPI, digRF, I2C,...) Specialties: Mapping communications and DSP algorithms into hardware. RTL (Verilog, VHDL) coding, Synthesis, timing closure, DFT (scan insertion, BIST, ATPG), simulation (RTL level, gate level, software/hardware co-simulation, AMS simulation), P&R (place and route), chip bring up and Lab testing, High speed low power DSP function design, CDC design, power gate, power domain design. SOC design (ARM, ARC, SPARC core with AMBA bus). Interface design (digRF, MIPI, SPI)