Chaitanya Neelamraju
About Chaitanya Neelamraju
Chaitanya Neelamraju is an FPGA Engineer Intern at Joby Aviation, where he has worked since 2019. He holds a Master's Degree in Computer Engineering from George Mason University and has experience as a Research Assistant at the same institution.
Work at Joby Aviation
Chaitanya Neelamraju has been working at Joby Aviation as an FPGA Engineer Intern since 2019. In this role, he focuses on enhancing the performance of various modules for Joby aircraft by utilizing Zynq FPGA technology. His contributions include developing methodologies for certification and improving system efficiency. He has worked extensively with technologies such as Xilinx Zynq7020, Xilinx Vivado, and various hardware description languages including VHDL and SystemVerilog. His work involves re-designing and verifying modules, such as an SPI module, using DO-254 coding techniques.
Education and Expertise
Chaitanya Neelamraju holds a Master’s Degree in Computer Engineering from George Mason University, where he studied from 2016 to 2018. Prior to this, he earned a Bachelor’s Degree in Electrical, Electronics, and Communications Engineering from Mahveer Institute of Science & Technology, JNTUH, from 2012 to 2016. His academic background provides a strong foundation in engineering principles, which he applies in his current role at Joby Aviation. He has expertise in FPGA design, verification processes, and various programming and design languages.
Research Experience at George Mason University
Chaitanya Neelamraju worked as a Graduate Research Assistant at George Mason University’s Volgenau School of Engineering from 2016 to 2018. During this period, he contributed to various research projects, focusing on the application of engineering principles in practical scenarios. He continued his association with the university as a Research Assistant from 2018 to 2019, where he further developed his skills and knowledge in engineering research and applications.
Technical Skills and Technologies
In his role at Joby Aviation, Chaitanya Neelamraju utilizes a range of technologies and tools. He has experience with Xilinx Vivado and SDK, HDL Design-Checker, and various coding techniques under the DO-254 standard. His technical skills include proficiency in VHDL, SystemVerilog, and Verilog, which are essential for FPGA design and verification. He has also explored advanced concepts such as pipelining and timing constraints to optimize algorithms, specifically the Cholesky algorithm.
Projects and Contributions
Chaitanya Neelamraju has made significant contributions to projects at Joby Aviation, particularly in the area of FPGA design. He developed a wrapper for modules to facilitate the use of records in AXI IP during the verification process with AXI VIP. Additionally, he worked on optimizing speed and timing for algorithms, demonstrating his ability to enhance system performance through innovative engineering solutions.