Chin Li Lo
About Chin Li Lo
Chin Li Lo is a Senior Principal Design Engineer at Rambus, where he has worked since 2021. He has extensive experience in engineering roles across several companies in Taiwan, including Huawei and Silicon Integrated Systems.
Work at Rambus
Chin Li Lo has been employed at Rambus as a Senior Principal Design Engineer since 2021. In this role, he contributes to the design and development of advanced technologies in the semiconductor industry. His position is based in Hsinchu County, Taiwan, where he applies his extensive engineering expertise to drive innovation within the company.
Previous Employment History
Prior to his current role, Chin Li Lo held several engineering positions across various companies. He worked at Silicon Integrated Systems as a Senior Engineer from 2001 to 2005. He then served as a Chief Engineer at Generalplus from 2009 to 2012. Following that, he was a Senior Engineer at Huawei's Hisilicon division from 2012 to 2018. He also worked as a Technical Manager at Creative Electronics from 2018 to 2019 and as an Engineer at PLDA from 2019 to 2021. Additionally, he was a Senior Engineer at Sunplus Technology from 2005 to 2008.
Education and Expertise
Chin Li Lo holds a Bachelor of Science degree in Computer Science and Information Engineering from National Chiao Tung University, where he studied from 1995 to 1999. He furthered his education by obtaining a Master of Science degree in Computer Science from National Chung Cheng University, completing his studies from 1999 to 2001. His academic background provides a solid foundation for his extensive career in engineering and technology.