Webber Kuo
About Webber Kuo
Webber Kuo is a Senior Project Engineer at Acer, where he has worked since 2016. He holds both a bachelor's and a master's degree in Information Engineering from National Taichung University of Science and Technology and has extensive experience in high-performance computing projects.
Work at Acer
Webber Kuo has been employed at Acer as a Senior Project Engineer since 2016. In this role, he has contributed to various high-performance computing (HPC) projects, utilizing advanced technologies and methodologies. His responsibilities include project planning, execution, and performance testing, ensuring that project requirements are met efficiently.
Education and Expertise
Webber Kuo completed his Bachelor's degree in Information Engineering at 國立台中科技大學 from 2010 to 2014. He further pursued a Master's degree in the same field at the same institution from 2014 to 2016. His academic background provides a strong foundation for his expertise in high-performance computing, network interfaces, and server architecture.
Technical Skills and Experience
Kuo has extensive experience in setting up and testing CPU cluster performance using Linpack and conducting performance tests with LAMMPS. He has expertise in configuring Mellanox InfiniBand (EDR) and Intel Omni-Path high-speed interconnect network interfaces. Additionally, he has worked with OpenStack software vendors for hardware and software validation.
Project Involvement
From 2017 to 2019, Webber Kuo participated in the Taiwan National Center for High-performance Computing (NCHC) HPC Project. He collaborated with NVIDIA to integrate NVIDIA vGPU technology into various projects, enhancing the capabilities of the systems involved. His role involved both technical implementation and performance optimization.
Industry Engagement
Kuo has presented product launches at exhibitions in Taiwan and internationally, showcasing the latest advancements in technology. He has engaged with global companies, including Intel, AMD, and NVIDIA, in x86 server hardware architecture planning and testing, contributing to the development of cutting-edge computing solutions.