Vivek Jayanand
About Vivek Jayanand
Vivek Jayanand is a SERDES Validation Engineer at Achronix Semiconductor Corporation, with extensive experience in post-silicon validation and debugging of semiconductor products. He holds a Master of Science in Electrical Engineering from the University of Southern California and has worked in various roles at companies such as Western Digital and Marvell Semiconductor.
Work at Achronix
Vivek Jayanand has been employed at Achronix Semiconductor Corporation as a SERDES Validation Engineer since 2022. In this role, he focuses on the validation of SERDES technology, contributing to the company's efforts in advancing semiconductor solutions. His position is based in Santa Clara, California, where he applies his expertise in post-silicon validation and functional debugging.
Education and Expertise
Vivek Jayanand earned a Master of Science (M.S.) degree in Electrical Engineering from the University of Southern California, studying from 1999 to 2000. His educational background provides a strong foundation for his extensive knowledge in semiconductor operations, including wafer fabrication, packaging, and failure analysis techniques. He has specialized skills in characterizing and compliance testing of PHYs for SATA, SAS, and PCIe standards.
Background
Vivek Jayanand has a diverse professional background in the semiconductor industry. He has held various positions at notable companies, including Western Digital and Marvell Semiconductor. His career spans roles such as Sr. Manager of SERDES Validation and Staff Field Applications Engineer, showcasing his progression in the field. He has accumulated significant hands-on experience in post-silicon validation and functional debugging of SERDES, PLLs, clocks, and memory buffer products.
Previous Experience
Prior to his current role, Vivek Jayanand worked at Western Digital in multiple capacities, including Principal Engineer on the Host Interface team and Sr. Manager of SERDES Validation. His tenure at Western Digital lasted from 2014 to 2022, during which he contributed to various projects related to PHY-based products. He also gained experience at Marvell Semiconductor as a Sr. Hardware Engineer and at Integrated Device Technology Inc as a Product Engineer.
Technical Skills
Vivek Jayanand possesses a comprehensive skill set in the semiconductor domain. He has expertise in post-silicon validation, functional debugging, and compliance testing of various standards. His knowledge extends to key aspects of semiconductor operations, including quality and reliability assessments. Additionally, he provides field application support to end customers, assisting them in resolving issues related to PHY-based products.