Aaditya Chaudhary
About Aaditya Chaudhary
Aaditya Chaudhary is a Design Engineer 2 at Ampere, with a background in electronics and computer engineering. He has experience in ASIC, SoC, and FPGA design, and has worked at various prestigious institutions including the Indian Institute of Management Bangalore and North Carolina State University.
Work at Ampere
Aaditya Chaudhary has been employed at Ampere as a Design Engineer 2 since 2021. In this role, he has been involved in various projects, including the verification of an I2C multiple bus controller and the functional verification of the LC3 Controller using the UVM Framework. His work also includes ASIC implementation of LSTM Cells and the development of a light runtime system for OpenCL on FPGA and GPU. His contributions focus on enhancing design and verification processes within the organization.
Education and Expertise
Aaditya Chaudhary completed his Bachelor of Technology (B.Tech.) in Electronics and Telecommunication Engineering at the National Institute of Technology Raipur from 2013 to 2017. He further pursued a Master of Science (MS) in Computer Engineering at North Carolina State University from 2019 to 2021. His graduate studies included specialized courses in ASIC, SoC, FPGA, and CPU/GPU architecture, equipping him with a strong foundation in hardware design and verification.
Background
Before his current role at Ampere, Aaditya Chaudhary gained diverse experience through various internships and research positions. He worked as a Summer Research Intern at Bhabha Atomic Research Centre in 2016 and held positions at North Carolina State University as a Graduate Student Researcher and Graduate Teaching Assistant in 2020. He also interned at Telcoma Technologies and was an Incubatee at the Indian Institute of Management Bangalore from 2017 to 2019.
Technical Skills and Tools
Aaditya Chaudhary possesses a range of technical skills relevant to his field, including proficiency in Verilog, System Verilog (UVM/OVM), C++, C, Python, Embedded C, CUDA, and OpenCL. He has hands-on experience with hardware interfacing using various FPGA platforms and tools such as Synopsys Design Compiler, Mentor Graphics Questasim/ModelSim, Xilinx Vivado, and Xilinx ISE. His practical knowledge extends to developing simulators for processors and cache systems.
Projects and Research Initiatives
Throughout his academic and professional career, Aaditya Chaudhary has engaged in several significant projects. He developed a MIPS-like 5-Stage Pipeline Processor Simulator and simulators for L1 and L2 Cache and Bus Based Cache Coherence. His projects also include implementing 2-D Convolution with Tiling and Coarsening and Radix Sort in OpenMP, showcasing his ability to apply theoretical knowledge to practical applications in hardware design and verification.