Essan Swain
About Essan Swain
Essan Swain is a CPU Verification Engineer with extensive experience in design engineering and verification, currently working at Ampere in Santa Clara, California. He has held various positions in notable companies such as AMD, Intel, and Texas Instruments, and has a strong academic background in electronics and computer engineering.
Current Role at Ampere
Essan Swain currently holds the position of CPU Verification Engineer at Ampere, where he has been employed since 2014. His role focuses on CPU front-end verification, contributing to the development and testing of CPU designs. With nearly a decade of experience in this position, he has developed automated diagnosis methodologies and tools for diagnosing functional issues in CAD technology.
Previous Experience at AMD
Prior to his current role, Essan Swain worked at AMD as a Senior Design Engineer starting in 2017. He had previously served as a Design Engineer 2 at AMD from 2015 to 2018. His tenure at AMD took place in Santa Clara, California, where he was involved in various design projects related to CPU technology.
Educational Background
Essan Swain completed his Bachelor of Engineering in Electronics at Birla Institute of Technology and Science, Pilani, from 2007 to 2011. He furthered his education by obtaining a Master's degree in Computer Engineering from the University of Wisconsin-Madison, where he studied from 2013 to 2015. Additionally, he attended Stanford University in 2016 for a brief period.
Internships and Early Career
Essan Swain began his career with various internships, including a Graduate Technical Intern position at Intel Corporation in 2014 and a Research and Development Intern role at Arm in 2015. He also gained experience as a Teaching Assistant at the University of Wisconsin-Madison in 2015. His early career included a project trainee position at IGCAR in 2009 and a design engineer role at Texas Instruments from 2011 to 2013.
Specialization and Contributions
Essan Swain specializes in CPU front-end verification and has been actively involved in the development of fault isolation CAD technology solutions. His expertise includes the creation of automated tools for diagnosing functional issues, which enhances the efficiency and reliability of CPU designs.