Gaurav Patil
About Gaurav Patil
Gaurav Patil is a Validation Engineer currently employed at Ampere in Santa Clara, California, where he has worked since 2021. He has previous experience at Qualcomm, Cadence Design Systems, and Strobe, Inc., and holds a Master of Science in Computer Engineering from Syracuse University.
Work at Ampere
Gaurav Patil has been employed at Ampere as a Validation Engineer since 2021. His role involves ensuring the reliability and performance of products through rigorous testing and validation processes. He is based in Santa Clara, California, where he contributes to the development of advanced computing solutions.
Previous Experience at Qualcomm
Prior to his current position, Gaurav worked at Qualcomm as a Senior Engineer from 2020 to 2021. During his one-year tenure in San Diego, California, he focused on projects related to semiconductor technology, contributing to the company's innovations in mobile and wireless communication.
Background in Firmware Development
Gaurav's early career included an internship at Strobe, Inc. in 2016, where he was involved in the development and testing of firmware for data processing and communication with LiDAR systems. This two-month internship took place in Los Angeles, California, and provided him with foundational experience in embedded systems.
Education and Expertise
Gaurav holds a Master of Science (M.S.) in Computer Engineering from Syracuse University College of Engineering and Computer Science, which he completed from 2015 to 2017. He also earned a Bachelor of Engineering (B.E.) in Electrical, Electronics and Communications Engineering from the University of Mumbai from 2011 to 2015. Additionally, he studied Electronics at Birla College of Arts, Science and Commerce from 2009 to 2011.
Career Progression in VLSI
Before his roles at Qualcomm and Ampere, Gaurav gained experience in VLSI design. He worked at Cadence Design Systems as Design Engineer II from 2017 to 2020 in San Jose, California. He also completed two internships at Eduvance, one as a Trainee in Backend VLSI in 2015 and another in Frontend VLSI in 2014, both in Mumbai, India.