Pranav Bhave
About Pranav Bhave
Pranav Bhave is an Architectural Design Verification Engineer currently working at Ampere in Santa Clara, California. He has a background in Electrical and Computer Engineering, with experience in design verification tools and advanced computer architecture concepts.
Work at Ampere
Pranav Bhave has been employed at Ampere as an Architectural Design Verification Engineer since 2020. His role involves ensuring the integrity and functionality of architectural designs through rigorous verification processes. He operates from Santa Clara, California, contributing to the development of advanced computing solutions. His expertise in design verification tools and methodologies supports the company's commitment to high-quality product development.
Previous Experience at Intel Corporation
Before joining Ampere, Pranav Bhave worked as a Graduate Technical Intern at Intel Corporation from 2019 to 2020 for a duration of eight months. This position was based in Hillsboro, where he gained valuable experience in the semiconductor industry. His internship provided him with hands-on exposure to various engineering practices and enhanced his technical skills in a professional environment.
Education and Expertise
Pranav Bhave holds a Bachelor of Engineering (BE) in Electrical, Electronics and Communications Engineering from the University of Pune, which he completed from 2013 to 2017. He furthered his education by obtaining a Master of Science (MS) in Electrical and Computer Engineering from Portland State University between 2018 and 2020. His academic background equips him with a solid foundation in advanced computer architecture concepts and design verification.
Technical Skills and Tools
Pranav Bhave possesses extensive knowledge of various design and verification tools, including Synopsys Design Compiler, Formality Checker, Prime Time, and Verdi. He is proficient in hardware description languages such as SystemVerilog and Verilog. His experience with emulators like Mentor Velocesolo and Synopsys Zebu, along with his skills in scripting with Python and programming in C and C++, further enhance his technical capabilities in the field.
Hands-On Experience and Methodologies
Pranav has gained practical experience in power supply and PCB debugging during a 9-month tenure as a Trainee Engineer in Power Electronics. He is knowledgeable in verification methodologies, including assertion-based verification, formal verification, and coverage analysis. His understanding of advanced concepts such as ASIC design flow, CDC, DDR, and memory controllers positions him as a competent professional in architectural design verification.