Tilak Miryala
About Tilak Miryala
Tilak Miryala is a Distinguished Engineer at Ampere, specializing in timing closure for complex chip designs. He has extensive experience in ASIC design and has held various engineering roles in the semiconductor industry across the United States and India.
Work at Ampere
Tilak Miryala has been serving as a Distinguished Engineer at Ampere since 2022. His role involves overseeing complex design projects and ensuring effective timing closure for large-scale integrated circuits. Prior to this position, he worked as a Senior Principal Design Engineer and as a Principal Design Engineer at Ampere, contributing to the development of advanced chip designs from 2017 to 2021. His experience at Ampere spans multiple roles, showcasing his expertise in timing closure and design methodologies.
Previous Experience in ASIC Design
Before joining Ampere, Tilak Miryala held the position of Lead ASIC Design Engineer at Open-Silicon from 2008 to 2015. His work involved leading design efforts for ASIC projects, focusing on timing closure and hierarchical designs. He also worked at AppliedMicro as a Senior Staff Design Engineer from 2015 to 2017, where he contributed to design strategies and methodologies. Additionally, he briefly served as a Synthesis & STA Consultant at SmartPlay Technologies in 2015.
Education and Expertise
Tilak Miryala earned his M.Tech in VLSI Design from the Indian Institute of Technology, Kharagpur, from 2006 to 2008. He completed his Bachelor of Engineering in Electronics and Communication at Osmania University from 2002 to 2006. His educational background provides a strong foundation for his expertise in ASIC design, particularly in timing closure for full chip hierarchical designs exceeding 70 million gates.
Specialized Skills in Design Engineering
Tilak Miryala specializes in timing closure for full chip hierarchical designs and has extensive experience in developing full chip constraints for complex chips with over 8000 clocks. He conducts logic equivalence checks and collaborates with physical design teams to enhance clock specifications. His skills include power analysis for pre-layout and post-layout designs, as well as leading teams focused on effective timing closure.