Udaya Bhaskara Kovvuri
About Udaya Bhaskara Kovvuri
Udaya Bhaskara Kovvuri is a Staff Engineer at Ampere in Santa Clara, California, specializing in power management and estimation methodologies. He holds a Master's degree in Electrical and Electronics Engineering from the University of South Florida and has extensive experience in various engineering roles across multiple companies.
Work at Ampere
Udaya Bhaskara Kovvuri has been employed at Ampere as a Staff Engineer since 2021. In this role, he focuses on power management tasks, utilizing a variety of tools including Joules and Voltus. His responsibilities include developing RTL and layout power estimation methodologies from scratch. He has been involved in post-silicon power feature validation and Vmin characterization, contributing to the company's efforts in optimizing power efficiency.
Education and Expertise
Udaya holds a Master's degree in Electrical and Electronics Engineering from the University of South Florida, where he studied from 2014 to 2016. He also earned a Bachelor's degree in Electrical, Electronics and Communications Engineering from Gandhi Institute of Technology & Management (GITAM) University in Visakhapatnam, studying from 2010 to 2014. His educational background is complemented by expertise in event-based architectural power modeling and estimation, as well as hands-on experience in power analysis and optimization.
Background
Before joining Ampere, Udaya worked at several notable companies in the semiconductor industry. He served as a Physical Design Engineer at Intel Corporation from 2016 to 2019 and as a Lead Design Engineer at Cadence Design Systems from 2019 to 2021. He also held positions at Soft Machines, where he worked as a Standard Cell Designer and Physical Design Engineer for a total of 15 months. His diverse experience spans various aspects of physical design and power management.
Technical Skills
Udaya possesses a strong skill set in scripting languages, including Verilog, System Verilog, Perl, Python, and Tcl. He is proficient in using industry-standard tools such as Voltus, PTPX, DC, ICC2, Genus, Innovus, Virtuoso, and Joules for power management tasks. His technical capabilities include conducting TDP validation using SIR benchmarks and performing performance-to-power analysis, as well as constructing V-f curves as part of CPU power optimization efforts.
Professional Achievements
Throughout his career, Udaya has made significant contributions to power management methodologies. He developed RTL and layout power estimation methodologies from scratch at Ampere, showcasing his ability to innovate in the field. His work in post-silicon power feature validation and Vmin characterization further highlights his commitment to enhancing power efficiency in semiconductor designs.