Mak Ajanovic
About Mak Ajanovic
Mak Ajanovic is a Software Engineering Manager (Diagnostics) at Arista Networks with extensive experience in hardware and software engineering.
Current Position at Arista Networks
Mak Ajanovic currently holds the position of Software Engineering Manager (Diagnostics) at Arista Networks, a role he has engaged in since 2021. In this capacity, he applies his extensive background in hardware and software engineering to manage diagnostics within the company. This role leverages his experience from previous positions and his expertise in signal integrity and compliance.
Software Engineering Career at Arista Networks
Before his current role, Mak Ajanovic served at Arista Networks in various capacities. He was a Software Engineer from 2017 to 2021, working in the San Francisco Bay Area. Prior to that, he contributed as a Hardware Test Engineer from 2015 to 2017, enhancing his skills in hardware testing and diagnostics. These roles have provided him with a broad perspective and deep insights into both hardware and software engineering.
Professional Experience at Cisco
Mak Ajanovic's career includes a significant role at Cisco, where he worked as a Hardware Engineer from 2014 to 2015 in San Jose, California. During this time, he deepened his expertise in hardware engineering, contributing to his overall knowledge and experience in the field.
Educational Background at UCSD
Mak Ajanovic earned a Bachelor of Science (BS) in Electrical and Computer Engineering from the University of California, San Diego (UCSD), studying from 2007 to 2012. His education laid the foundation for his career, providing him with the knowledge and skills necessary to excel in various engineering roles. His academic background is complemented by research in radiation hardening for satellite radios and designing FPGA for high-speed RF applications in the defense industry.
Early Career and Internships
Mak Ajanovic’s early career included internships and freelance positions that provided a strong foundation for his engineering career. He interned as a Hardware Design Engineer at Vulcan Wireless from 2011 to 2012 and worked as a Freelance IT Consultant in the Portland, Oregon Area from 2004 to 2005. Additionally, he volunteered at Free Geek from 2003 to 2004, gaining valuable experience that would later benefit his professional roles.
Technical Expertise in Signal Integrity and Safety Verification
Mak Ajanovic has built a reputation for his technical expertise, particularly in PHY signal integrity analysis for various Ethernet standards, including 10/100/1G/2.5G/5G/10G copper and 1G/10G SFP(+) fiber signals. He is experienced in compliance and safety verification, including Hipot testing and Cable Discharge Events. He also has experience characterizing and debugging UPoE ripple/noise and LLDP for power levels up to 60W. These skills have been pivotal in his engineering roles, enabling him to ensure high standards of safety and performance.