Pela Cefalas
About Pela Cefalas
Pela Cefalas is a Hardware Design Engineering Intern at Arista Networks and an RF Engineer at Apple, with a background in Electrical Engineering from the University of Waterloo.
Current Position at Apple
Pela Cefalas is currently employed at Apple as an RF Engineer. He has held this position since 2018 and is based in Cupertino.
Current Position at Arista Networks
Pela Cefalas is working as a Hardware Design Engineering Intern at Arista Networks. He has been in this role since 2017 and is based in Santa Clara.
Previous Internships and Roles
Pela Cefalas has amassed diverse experience through various internships and roles. He worked at Apple as an RF Design Intern in 2017 for a 3-month stint in Cupertino. He also held a similar role at Arista Networks as a Hardware Design Engineering Intern in 2016 for three months in Santa Clara. In 2015, he served as a Signals Engineering Assistant at Toronto Transit Commission (TTC) for a duration of three months. Earlier that same year, he worked as a Developer at AppCentrica Inc. for three months. In 2014, Pela had a three-month stint with TTC where he contributed as a C#.NET, Oracle, and Crystal Reports Developer.
Educational Background
Pela Cefalas holds a Bachelor's Degree in Electrical Engineering from the University of Waterloo. He completed his studies over a period of five years, from 2013 to 2018.