Zev Gross C.I.D
About Zev Gross C.I.D
Zev Gross C.I.D is a Senior PCB Designer at Arista Networks with extensive experience in high-density, high-speed multi-layer PCB design.
Title and Current Position
Zev Gross C.I.D currently holds the position of Senior PCB Designer at Arista Networks. Stationed in Santa Clara, CA 95054, he has served in this role since 2016. As a senior professional, he is responsible for designing complex printed circuit boards (PCBs) that meet high-density and high-speed requirements.
Professional Experience
Zev Gross C.I.D brings considerable experience in PCB design from multiple companies. Before his tenure at Arista Networks, he worked at Sparton Corporation as a Senior PCB Designer from 2015 to 2016 in the San Francisco Bay Area. Prior to that, he served as a Senior PCB Designer at Hunter Technology from 2013 to 2015 in Milpitas, CA. His career includes notable stints at NBS Design, ZMG PCB Design, and Adcom Ltd among others, where he gained experience in diverse applications and technologies.
Education and Certifications
Zev Gross C.I.D studied engineering at ORT Colleges, where he completed his education and achieved his Professional Engineer (PE) certification from 1988 to 1991. His educational background laid the foundation for his extensive knowledge and skills in PCB design.
PCB Design Expertise
Zev Gross C.I.D specializes in designing high-density, high-speed multi-layer PCBs with up to 18 layers and 15,000 pads. His designs encompass a variety of applications, including motherboards, backplanes, PCIE cards, power boards, and handheld devices with RF capabilities. He uses advanced techniques such as blind and buried vias, laser vias, and manages large BGA pin counts to achieve optimal design.
Technical Skills and Tools
Proficient in using Cadence Allegro and OrCad Capture for PCB design and schematic capture, Zev Gross C.I.D is well-versed in controlled impedance routing across technologies like RF, analog, digital, and high-speed wireless. He utilizes Polar tools for building stack-ups and calculating controlled impedance and employs Valor Trilogy for checking short and disconnected nets in PCBs. Additionally, he has expertise in producing production-ready files in ODB++ format and managing constraints such as differential pairs and matched length for signals.