Jianfeng Zhang
Senior Fpga Design Engineer @ ASML
About Jianfeng Zhang
Jianfeng Zhang is a Senior FPGA Design Engineer at ASML in San Jose, California, with expertise in designing and verifying RTL Verilog/VHDL for FPGA applications. He holds a Master's Degree in Computer Engineering from New York University and a Bachelor's Degree in Electrical and Electronics Engineering from the University of Electronic Science and Technology of China.