Yao Hsien Wang

Yao Hsien Wang

Senior Hardware Engineer @ ASRock Rack

About Yao Hsien Wang

Yao Hsien Wang is a Senior Hardware Engineer with extensive experience in designing server motherboards and system hardware for Intel and AMD platforms. He has worked at notable companies such as Foxconn, ASRock Rack, and Pegatron Corporation, and possesses a strong understanding of high-speed serial bus technologies.

Work at ASRock Rack

Yao Hsien Wang has been employed at ASRock Rack as a Senior Hardware Engineer since 2017. In this role, he focuses on designing server motherboards and system hardware specifically for Intel Xeon Scalable and AMD EPYC x86 platforms. His responsibilities include collaborating with cross-functional teams, such as validation and BIOS/BMC/ME teams, to identify and resolve design issues during the development process. His expertise in high-speed serial bus technologies is integral to his work at ASRock Rack.

Previous Experience at Foxconn

Before joining ASRock Rack, Yao Hsien Wang worked at Foxconn as a Senior Hardware Engineer for a duration of 10 months in New Taipei City from 2016 to 2017. His role involved hardware engineering tasks that contributed to the company's projects during his tenure.

Background in Hardware Engineering

Yao Hsien Wang has a diverse background in hardware engineering, having worked at several companies in various capacities. He served as a Section Manager of Hardware Engineering R&D at Pegatron Corporation from 2013 to 2016 and as a Senior Hardware Engineer R&D from 2008 to 2013. Earlier in his career, he worked at Ritek Corporation as a Hardware Engineer from 2006 to 2007. This extensive experience has equipped him with a strong foundation in hardware design and development.

Education and Expertise

Yao Hsien Wang studied at National Yunlin University of Science and Technology from 2004 to 2006. He possesses a strong understanding of high-speed serial bus technologies, including SATA, PCIe, and USB, as well as parallel bus DDR4. His technical skills also include developing Lattice CPLD coding using Verilog, which enhances his capabilities in hardware design.

Research and Development Contributions

In his current and previous roles, Yao Hsien Wang has been involved in the research and development of circuit architectures for various server configurations, including 1U, 2U, and 4U levels. His contributions to R&D efforts have played a significant role in advancing hardware solutions in the industry.

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