Aditya Hendra
About Aditya Hendra
Aditya Hendra is an ASIC Verification Engineer at Axis Communications in Lund, Sweden, with over 7 years of experience in the field. He holds a Bachelor's degree in Computer Science and Mathematics from Universitas Bina Nusantara and a Master's degree in Embedded Systems from Uppsala University.
Work at Axis Communications
Aditya Hendra has been employed at Axis Communications since 2016, serving as an ASIC Verification Engineer. In this role, he contributes to various innovative projects within the company, which is recognized for its strong presence in the tech industry. His work focuses on ensuring the reliability and performance of ASIC designs, leveraging his expertise in verification engineering.
Education and Expertise
Aditya Hendra holds a Bachelor's degree in Computer Science and Mathematics from Universitas Bina Nusantara (Binus), where he studied from 2001 to 2007. He furthered his education at Uppsala University, earning a Master's degree in Embedded Systems from 2013 to 2015. His academic background provides a solid foundation for his specialization in ASIC verification.
Background in ASIC Verification Engineering
With over 7 years of experience in ASIC verification engineering, Aditya Hendra has developed a strong skill set in the field. His expertise includes constraint random verification, utilizing the SystemVerilog UVM framework. This specialization allows him to effectively validate complex ASIC designs, contributing to the overall success of projects at Axis Communications.
Professional Experience Timeline
Aditya Hendra's professional journey in ASIC verification engineering began after completing his Bachelor's degree in 2007. He gained significant experience over the years, culminating in his current position at Axis Communications, where he has worked for 8 years since 2016. His continuous development in the field reflects his commitment to advancing his skills and knowledge.