Kenneth Hermann
About Kenneth Hermann
Kenneth Hermann is a Senior ASIC Engineer at Boston Scientific with extensive experience in pre-silicon verification, FPGA targeting, and post-silicon validation.
Company
Kenneth Hermann currently works at Boston Scientific as a Senior ASIC Engineer. He has been with the company since 2014 and is based in Santa Clarita, California, United States.
Title
Kenneth Hermann holds the position of Senior ASIC Engineer at Boston Scientific. His responsibilities likely encompass the design and verification of ASIC components, leveraging extensive pre-silicon and post-silicon verification experience.
Education and Expertise
Kenneth Hermann has a diverse educational background in electrical and computer engineering. He earned a Bachelor of Science degree from Missouri University of Science and Technology in Electrical Engineering (1980-1983) and subsequently obtained a Master of Science in Electrical Engineering from the same institution (1983-1985). Later, he pursued further education at Santa Clara University, acquiring a Master of Science in Computer Engineering (2002-2004) and an ASIC Design & Test Certificate (2004-2005). He also attended the University of Santa Cruz Extension in Silicon Valley, where he studied VLSI in 2010-2011.
Professional Background
Kenneth Hermann has extensive professional experience across multiple high-tech companies. Notable positions include Senior Verification Engineer at QLogic in Roseville, CA (2011-2014), Component Design Engineer at Intel in Hillsboro, OR (2006-2010), and several roles as a Staff FPGA and Hardware Engineer at companies like Maple Optical Systems, Tiara Networks, Ericsson, Qualcomm, and Larus Corporation. His career began as a Senior Hardware Engineer at TRW-ESL in Sunnyvale, CA (1985-1994).
Technical Skills and Tools
Kenneth Hermann is proficient in pre-silicon verification processes, including full chip and block test plans, test benches, and directed/constrained-random tests using System Verilog/UVM. He has experience targeting Xilinx, Altera, and Actel FPGAs. Additionally, he has performed FPGA synthesis, layout/floor plan, place & route, and timing closure. His post-silicon validation skills include lab and tester floor activities. He utilizes simulators such as Cadence Incisive/IUS, Mentor Modelsim/Questa, Synopsys VCS, and Springsoft Debussy/Verdi. For synthesis and place & route, he employs tools like Synopsys SynplifyPro, Xilinx ISE, and Altera Quartus, and uses version control systems like CVS, Subversion, and Mercurial. He also leverages Spyglass for linting and Trac for issue tracking.