Dave Kaplan
About Dave Kaplan
Dynamic, people-oriented Process Design Kit and EDA engineer with more than 13 years of experience with Cadence Custom IC products. Industry expert on Virtuoso 6.1 deployment, adoption, and training. Strong sales and program management background and understanding of physical design applications and design-for-manufacturing applications. Accomplished applications engineer, seasoned presenter and expert in technical presentation, training development and delivery. Areas of Knowledge/Experience: Specialties: • Team and project management • Technical sales • Public speaking / presentation • Diverse technical background • Excellent communication skills • Training program development Programming: • SKILL/SKILL++, Relative Object Design (ROD), Parameterized Cells, Abutment, • SKILL Advanced Data Structures, User Interface • Perl • HTML / Perl CGI • C Shell and K Shell scripting • C/C++ (proficient) • Python/Pycells (proficient) • Open Access API scripting and C++ interface (proficient) Back-end EDA/PDK: • Virtuoso Layout, Turbo Toolbox, Virtuoso XL, Qcells • Virtuoso Floorplanner, Custom Placer • Cadence Space-based Router • Cadence Chip Optimizer General EDA: • ASIC/SOC flow architecture and product integration • Technology file construction and optimization, including design rules • Process Design Kit creation, maintenance, and automation • Component Description Format (CDF) • Extensive UI customization and custom application development • Registry and installation maintenance for 3rd-party applications • Integrators’ Toolkit (ITK) • OpenAccess API scripting (proficient) Front-end (some experience): • Composer schematics, Analog Design Environment L, XL, Spectre • Constraint-driven editing, Circuit Prospector