Bhanu Pratap Singh Negi
About Bhanu Pratap Singh Negi
Bhanu Pratap Singh Negi is a Senior Manager in ASIC Design at Espressif Systems, with extensive experience in the semiconductor industry, including previous roles at Marvell Semiconductor and SiRF Technology. He holds a B Tech in Electronics and Communication Engineering and has expertise in various design and verification processes, as well as low power design methodologies.
Current Role at Espressif Systems
Bhanu Pratap Singh Negi serves as Senior Manager ASIC Design at Espressif Systems, a position he has held since 2021. In this role, he oversees ASIC design projects and manages a team focused on developing advanced semiconductor solutions. His responsibilities include leading design initiatives, ensuring adherence to project timelines, and implementing effective design methodologies.
Previous Experience at Marvell Semiconductor
Negi worked at Marvell Semiconductor from 2009 to 2018, where he progressed from Staff Engineer to Senior Staff Engineer. During his tenure, he contributed to various ASIC design projects, focusing on enhancing chip performance and reliability. His experience at Marvell included working in the Pune area of India, where he developed skills in timing analysis and design for testability (DFT).
Background in ASIC Design
Negi began his career in ASIC design at SiRF Technology India Pvt Ltd, where he worked as a Senior Engineer from 2006 to 2009. He gained valuable experience in chip design and verification processes. Prior to that, he was employed at HCL Tech as a Member of Technical Staff (MTS) from 2004 to 2006, further solidifying his foundation in electronics and communication engineering.
Education and Expertise
Negi earned his Bachelor of Technology (B Tech) degree in Electronics and Communication Engineering from Govind Ballabh Pant Krishi Evam Praudyogik Vishwavidyalaya, completing his studies from 1999 to 2003. His educational background provides a strong foundation for his extensive knowledge in MIPI DSI, PHY specifications, and Bluetooth standards, including BLE (BT 4.0).
Technical Skills and Contributions
Negi possesses hands-on experience with the Palladium XP emulation platform, focusing on generating full chip databases and conducting full chip static timing analysis (STA) for DFT modes. He has been involved in the initial silicon bring-up process, verifying chip functionalities, and assisting firmware teams in debugging. His expertise includes low power check signoff on multiple SoCs and developing full chip DFT schemes.