Sampanna Pathak
About Sampanna Pathak
Sampanna Pathak is a Hardware Design Engineer with extensive experience in high-frequency custom clock cells and power grid design. He has worked at notable companies such as AMD, Oracle, and Flex Logix Technologies, contributing to various advanced technology nodes.
Work at Flex Logix Technologies
Sampanna Pathak has been employed at Flex Logix Technologies, Inc. as a Hardware Design Engineer since 2017. In this role, he has contributed to the RTL2GDS flow for embedded FPGA IP and edge AI chip development. His work involves the application of advanced design methodologies and tools to enhance the performance and efficiency of hardware systems.
Previous Experience at Oracle
Prior to his current position, Sampanna Pathak worked at Oracle America Inc. in various capacities. He served as a Hardware Design Engineer from 2014 to 2016, where he focused on power grid design and power optimizations for 10nm and 7nm SPARC cores. He later advanced to the role of Senior Hardware Design Engineer from 2016 to 2017, contributing to the physical design of high-frequency custom clock cells.
Internship at AMD
Sampanna Pathak completed a four-month internship at AMD in 2014, based in Sunnyvale. During this internship, he gained practical experience in hardware design, which laid the foundation for his subsequent career in the semiconductor industry.
Education and Expertise
Sampanna Pathak holds a Master of Science (M.S.) in Electrical and Electronics Engineering from the University of Southern California, where he studied from 2012 to 2014. He also earned a Bachelor of Engineering (B.E.) in Electrical, Electronics and Communications Engineering from the Maharashtra Institute of Technology, from 2008 to 2012. His academic background has equipped him with expertise in DFT pattern generation for embedded FPGA IP and functional verification.
Technical Skills and Projects
Sampanna Pathak has developed a strong skill set in hardware design, with experience across multiple technology nodes, including 40nm, 28nm, 16nm, 12nm, and 7nm designs. He has utilized programming languages such as Python, Perl, and Tcl to create automation scripts for analyzing timing critical paths and optimizing power usage. Additionally, he has participated in open projects related to deep learning, big data, and machine learning.