Satheesh Nataraja Pillai
About Satheesh Nataraja Pillai
Satheesh Nataraja Pillai serves as the Director of Engineering for SOC and IP Subsystem Physical Design at Flex Logix Technologies, Inc., where he has worked since 2021 in Mountain View, California. With extensive experience in the semiconductor industry, he has held various engineering roles at notable companies including Intel Corporation and ST-Ericsson.
Work at Flex Logix Technologies
Satheesh Nataraja Pillai serves as the Director of Engineering for SOC and IP Subsystem Physical Design at Flex Logix Technologies, Inc. since 2021. In this role, he focuses on overseeing the physical design aspects of system-on-chip (SOC) and intellectual property (IP) subsystems. His leadership contributes to the company's efforts in developing advanced semiconductor solutions in Mountain View, California.
Previous Experience at Intel Corporation
Before joining Flex Logix, Satheesh worked at Intel Corporation for a total of 16 years in various capacities. He served as an Engineering Team Lead for Physical Design, DFT, and Verification from 2001 to 2009 in Bengaluru, India. He later returned to Intel as a Senior Engineering Manager for SOC and IP Physical Design from 2013 to 2021 in Santa Clara, California, where he managed teams and projects focused on enhancing physical design methodologies.
Education and Expertise
Satheesh Nataraja Pillai obtained his M.Tech degree in Solid State Technology from the Indian Institute of Technology, Madras, from 1998 to 2000. His educational background provides a strong foundation in semiconductor technology, which he has applied throughout his career in various engineering roles across multiple companies.
Achievements in Physical Design
Throughout his career, Satheesh has made significant contributions to physical design methodologies. He architected a low-cost, die area-efficient System on Chip (SOC) using the TSMC N6 process node. He also defined a Network on Chip (NOC) integration strategy and developed methodologies to optimize power, performance, and area (PPA) metrics, enhancing chip competitiveness.
Career Overview and Other Roles
In addition to his roles at Intel, Satheesh has held various engineering positions at other notable companies. He worked as an Engineering Lead at Future Technology Devices International for 7 months in Singapore, and as a Design Manager at ST-Ericsson from 2009 to 2012. He also served as a Lead Technical Consultant at Broadcom Inc. for 5 months in 2013, and as a Design Engineer at Motorola Semiconductor for 1 year in 2000.