Erich Fries
About Erich Fries
Erich Fries is a Sr. Design Engineer with extensive experience in ASIC design, currently working at HP and General Atomics in the Greater San Diego Area. He has a strong background in organizing design work and documentation, having designed over 50 logic modules without any chip re-spins.
Work at General Atomics
Erich Fries has been employed at General Atomics as a Senior Design Engineer since 2019. In this role, he has contributed to various engineering projects within the Greater San Diego Area. His responsibilities include designing and documenting complex systems, ensuring high standards of quality and performance in his work.
Experience at HP
Fries has worked at HP as an ASIC Design Engineer since 2002. With over 22 years of experience in this position, he has developed expertise in application-specific integrated circuits, contributing to the design and implementation of various electronic components in the Greater San Diego Area.
Previous Role at Cadence Design Systems
Prior to his current positions, Erich Fries worked at Cadence Design Systems from 1995 to 2002 as a Senior Member of Consulting Staff and Technical Manager. During his seven years there, he gained significant experience in design engineering and project management, further enhancing his skills in the field.
Education and Expertise
Erich Fries earned a Bachelor of Science degree from Fresno State. His educational background has provided him with a solid foundation in engineering principles, which he has applied throughout his extensive career in design engineering.
Design Contributions and Achievements
Fries has designed over 50 logic modules, including a floating-point multiplier and an AXI bus aggregator. He is recognized for his ability to organize design work and maintain detailed documentation. Notably, he has never experienced a chip re-spin due to any of his designs, reflecting his commitment to quality and precision in engineering.