Krishnaraj Varma
About Krishnaraj Varma
Krishnaraj Varma is a Principal Communication Systems Engineer at Impinj, with extensive experience in digital signal processing and communications. He has held various roles in academia and industry, including positions at Virginia Tech, Tata Consultancy Services, Hughes Network Systems, and Qualcomm.
Work at Impinj
Krishnaraj Varma has been employed at Impinj as a Principal Communication Systems Engineer since 2017. In this role, he focuses on the development and implementation of communication systems, leveraging his extensive background in digital signal processing and hardware architecture design.
Education and Expertise
Krishnaraj Varma holds a PhD in Electrical Engineering from Virginia Tech, where he studied from 2003 to 2006. He also earned a Master of Science in Electrical Engineering from the same institution, completing his studies from 2000 to 2002. Additionally, he obtained a Bachelor of Technology in Applied Electronics & Instrumentation Engineering from the College of Engineering Trivandrum, studying from 1993 to 1997.
Background
Krishnaraj Varma began his career as an intern at National Aerospace Laboratories in 1996. He then worked at Tata Consultancy Services as a Consultant in Market Regulation Software from 1998 to 2000. He returned to Virginia Tech as a Graduate Research Assistant and later served as an Instructor in Digital Signal Processing and Filter Design in 2005.
Professional Experience
Krishnaraj Varma has held various engineering roles, including Principal Engineer at Hughes Network Systems from 2006 to 2012 and Senior Staff Engineer at Qualcomm from 2012 to 2017. His experience spans over two decades in the field of communication systems and digital signal processing.
Technical Skills
Krishnaraj Varma possesses strong simulation skills in Matlab and is proficient in object-oriented programming languages such as C++, SystemC, and Python. He has in-depth knowledge of the latest WiFi standards, including 802.11ac Wave-2 and 802.11ax, and has experience in Verilog HDL. His research experience includes array processing and designing efficient architectures for image coding systems.