Lee Burns
About Lee Burns
Lee Burns is a Principal RTL Design Engineer at Impinj, with extensive experience in electrical engineering and design. He has held significant roles at companies such as Lumotive, Cypress Semiconductor, MicroVision, and Boston Scientific, focusing on low-power applications and interactive video projection projects.
Work at Impinj
Lee Burns has been serving as a Principal RTL Design Engineer at Impinj since 2023. In this role, he focuses on RTL design for low-power applications, contributing to the company's advancements in RFID technology. His expertise in physical design tasks and co-simulation using Python/System Verilog enhances the efficiency of design processes within the organization.
Previous Experience at Lumotive
Prior to joining Impinj, Lee Burns worked at Lumotive as a Principal Electrical Engineer from 2020 to 2022. During his tenure in Bellevue, Washington, he was involved in interactive video projection projects utilizing MEMs and lasers, showcasing his skills in innovative electrical engineering applications.
Experience at Cypress Semiconductor Corporation
Lee Burns held the position of Electrical Design Engineer Principal at Cypress Semiconductor Corporation from 2010 to 2017. Based in Lynnwood, Washington, he worked on mass-produced consumer chips, specifically the Cypress PSOC. His role involved utilizing Continuous Integration tools such as Buildbot and Mercurial to streamline design processes.
Educational Background
Lee Burns studied at the University of Washington, where he earned a Master of Medical Engineering (MME) from 1998 to 2002. He also completed a Bachelor of Science in Electrical Engineering (BSEE) from the same institution, studying from 1987 to 1991. His educational background supports his expertise in electrical engineering and medical applications.
Specialization and Skills
Lee Burns specializes in RTL design for low-power applications and possesses extensive skills in standard cell library design, layout, and characterization. He is proficient in physical design tasks, including layout, place and route, DRC, LVS, and clock tree synthesis. His experience also includes Power Aware Logic verification and contributions to the development of ASICs and FPGAs for high-reliability medical applications.