Phillip Pan
About Phillip Pan
Phillip Pan is a Hardware Development Engineer with extensive experience in high-speed CPU board design and embedded systems. He has worked for notable companies including Cisco Systems, Apple, and Joby Aviation, specializing in signal and power integrity.
Work at Joby Aviation
Phillip Pan has been employed at Joby Aviation as a Hardware Development Engineer since 2019. In this role, he focuses on the design and development of hardware systems, contributing to the company's innovative projects in the aviation sector. His work is centered in the San Francisco Bay Area, where he collaborates with a team dedicated to advancing electric vertical takeoff and landing (eVTOL) aircraft technology.
Previous Experience at Cisco Systems
Before joining Joby Aviation, Phillip Pan worked at Cisco Systems from 2006 to 2013 as a Technical Leader. His responsibilities included co-designing system-on-chip (SoC) packages and printed circuit boards (PCBs), with a strong emphasis on signal and power integrity. This position allowed him to develop expertise in complex system design, which he later applied in his subsequent roles.
Experience at Apple
Phillip Pan served as a Hardware Design Engineer at Apple from 2015 to 2019. During his tenure, he focused on the design of hardware components, contributing to the development of high-performance consumer electronics. His role involved ensuring the integrity and efficiency of hardware designs, which are critical in Apple's product offerings.
Education and Expertise
Phillip Pan holds a Master of Science (M.S.) degree in Electrical Engineering from the University of Southern California. His academic background supports his specialization in high-speed CPU boards and embedded systems. He possesses extensive knowledge in signal and power integrity, high-speed memory modeling, and simulations, utilizing various industry-standard tools such as HSPICE and PowerSI.
Career at Cadence Design Systems
From 2014 to 2015, Phillip Pan worked at Cadence Design Systems as a Principal Design Engineer. His role involved developing LPDDR/DDR interfaces and test boards, focusing on signal integrity (SI) and power integrity (PI). This experience further enhanced his skills in chip and package co-design, contributing to his comprehensive understanding of hardware development.