Andrew Wendt
About Andrew Wendt
Andrew Wendt is a Design Engineer at ON Semiconductor in Pocatello, Idaho, where he specializes in digital mixed-signal ASIC production and conducts static timing analysis for timing closure. He has a Bachelor of Science degree from Brigham Young University and has been in his current role since 2015.
Work at ON Semiconductor
Andrew Wendt has been employed at ON Semiconductor since 2015, serving as a Design Engineer. His role involves conducting static timing analysis (STA) to achieve timing closure following automatic place and route processes. He is responsible for design for test (DFT) and functional pattern generation, which are critical for silicon verification. Wendt engages in bench evaluation of digital components to confirm system functionality, ensuring that the designs meet operational standards.
Education and Expertise
Andrew Wendt earned a Bachelor of Science (B.S.) degree from Brigham Young University, completing his studies over a nine-year period from 2006 to 2015. His educational background provides a foundation for his expertise in digital mixed-signal ASIC production. Wendt specializes in the design of digital systems, utilizing custom RTL and IP blocks to create effective solutions in his field.
Background
Andrew Wendt has a background in digital system design, with a focus on mixed-signal ASIC production. His experience includes the use of SystemVerilog test benches and UVM for the verification of custom digital systems. Wendt's knowledge extends to performing synthesis and DFT insertion, which are essential for maintaining the integrity of custom digital designs.
Technical Skills
Andrew Wendt possesses a range of technical skills relevant to his role as a Design Engineer. He is proficient in conducting static timing analysis, which is crucial for ensuring timing closure in digital designs. His expertise includes the generation of functional patterns for silicon verification and the evaluation of digital systems to ensure their functionality. Wendt's use of SystemVerilog and UVM highlights his capability in verifying complex digital systems.