Dheeraj.N. Kulal
About Dheeraj.N. Kulal
Dheeraj N. Kulal is a Design Layout Engineer at ON Semiconductor in Bengaluru, India, with expertise in integrated circuit layout design and timing optimization. He holds degrees from Alva's College of Education and Dr. Ambedkar Institute of Technology, and has experience in PnR and STA processes.
Work at ON Semiconductor
Dheeraj N. Kulal has been employed at ON Semiconductor as a Design Layout Engineer since 2019. He works in the Bengaluru Area, India, where he focuses on developing layout designs for complex integrated circuits. His responsibilities include handling Place and Route (PnR) and Static Timing Analysis (STA) processes. Kulal's role involves optimizing circuit timing by reducing parasitics, which is crucial for enhancing the performance of semiconductor devices.
Education and Expertise
Dheeraj N. Kulal completed his Pre University education at Alva's College of Education from 2012 to 2014. He then pursued a degree at Dr. Ambedkar Institute of Technology, achieving a GPA of 8.9 from 2014 to 2018. Prior to this, he attended Sri Laxmi Janardhan School, where he achieved a perfect CGPA in his X Std examinations. His academic background provides a strong foundation for his expertise in semiconductor design, particularly in addressing Length of Diffusion (LOD) and Shallow Trench Isolation (STI) effects.
Background
Dheeraj N. Kulal began his career as an IC Layout Engineer (Trainee) at RV-VLSI VLSI and Embedded Systems Design Center in 2019. He worked there for seven months in Bangalore Urban, Karnataka, India, gaining initial experience in the field of integrated circuit design. This early exposure contributed to his development as a skilled engineer in layout design and semiconductor processes.
Technical Skills and Specializations
Dheeraj N. Kulal possesses specialized skills in developing layout designs for various complex integrated circuits, including Phase-Locked Loops (PLL), Modulators, Deserializers, Power-On Reset (POR) circuits, and Low Dropout Regulators (LDO). His technical expertise includes proficiency in Place and Route (PnR) and Static Timing Analysis (STA), as well as a strong focus on optimizing circuit performance by managing parasitics.