Dorin Moise
About Dorin Moise
Dorin Moise is a Layout Engineer at ON Semiconductor in Bucharest, Romania, where he has worked since 2008. He specializes in mask layout design and verification processes, ensuring that integrated circuit designs meet schematic specifications.
Work at ON Semiconductor
Dorin Moise has been employed at ON Semiconductor since 2008, serving as a Layout Engineer for 16 years. His role is based in Bucharest, Romania, where he focuses on ensuring that integrated circuit designs align with schematic design specifications. His responsibilities include overseeing the entire layout design flow, from schematic to layout generation.
Education and Expertise
Dorin Moise studied at The Faculty of Electrical Engineering and Computer Science in Brasov. His educational background provides a strong foundation for his work in integrated circuit design and layout engineering. He specializes in mask layout design and verification processes, which encompass Design Rule Checking (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and Design for Manufacturability (DFM).
Background
Dorin Moise has a professional background in layout engineering, with a focus on integrated circuit design. His extensive experience in the field enables him to effectively manage the layout design flow, ensuring compliance with industry standards and specifications. His work contributes to the overall quality and reliability of semiconductor products.
Achievements in Layout Design
Dorin Moise has demonstrated proficiency in completing the layout design flow, which includes critical processes such as schematic design and layout generation. His expertise in mask layout design and verification processes has been instrumental in maintaining high standards in integrated circuit design at ON Semiconductor.