Fadillah Harun
About Fadillah Harun
Fadillah Harun is a Probe Test Engineer at ON Semiconductor, specializing in device performance monitoring and quality issue resolution. He previously worked as a Probe Card Hardware Engineer at NXP Semiconductors, where he collaborated with engineers on device qualification and yield enhancement projects.
Work at Onsemi
Fadillah Harun has been employed at ON Semiconductor as a Probe Test Engineer since 2017. In this role, he focuses on various aspects of probe testing, contributing to the overall efficiency and effectiveness of semiconductor testing processes. His work involves collaboration with cross-functional teams to ensure high-quality outcomes in device performance.
Previous Experience at NXP Semiconductors
Before joining ON Semiconductor, Fadillah worked at NXP Semiconductors as a Probe Card Hardware Engineer from 2015 to 2017. During his two years in this position, he was based in Selangor, Malaysia. His responsibilities included collaborating with FAB and Product Engineers to identify root causes of quality issues on wafers, enhancing the reliability of semiconductor devices.
Education and Expertise
Fadillah Harun earned a Bachelor of Photonic Engineering from Universiti Malaysia Perlis, where he studied Laser and Optical Engineering from 2011 to 2015. His educational background provides him with a solid foundation in photonics, which is essential for his work in semiconductor testing and engineering.
Technical Skills and Specializations
Fadillah specializes in monitoring device performance on Eagle tester platforms, specifically the ETS200 and ETS364, with a focus on MOSFET and BUMP devices. He has experience using Mentographic for Pads Logic and Pads Layout, which supports his technical capabilities in probe testing and device qualification.
Involvement in Projects
Fadillah has been involved in site migration projects aimed at enhancing device performance and yield. These projects include initiatives for test time reduction, demonstrating his commitment to improving operational efficiency within the semiconductor testing environment.