Harish Kandibanda
About Harish Kandibanda
Harish Kandibanda is a Principal Design Engineer at onsemi in San Jose, California, where he has worked since 2019. He holds a Master's degree in VLSI design from the University of Cincinnati and has expertise in designing RX MIMO RTL for Baseband ICs.
Work at Onsemi
Harish Kandibanda has been employed at Onsemi as a Principal Design Engineer since 2019. He operates from the company's office located in San Jose, California. In this role, he focuses on various aspects of design engineering, particularly in the field of VLSI design. His responsibilities include overseeing design accuracy and efficiency, particularly in the context of RX MIMO netlists.
Education and Expertise
Harish Kandibanda earned a Master's degree in VLSI design from the University of Cincinnati - College of Engineering and Applied Science, completing his studies from 2017 to 2019. He also holds a Bachelor's degree from Karunya Institute of Technology and Sciences, which he obtained from 2008 to 2012. His educational background supports his expertise in designing RX MIMO RTL for Baseband ICs and advanced signal processing.
Previous Experience at Xilinx
Before joining Onsemi, Harish Kandibanda worked as a Senior Design Engineer at Xilinx for a period of seven months in 2018 to 2019. His role involved contributing to design projects in San Jose, California, where he applied his skills in VLSI design and signal processing.
Technical Skills and Specializations
Harish Kandibanda specializes in ECO implementation and LEC checks on RX MIMO netlists. He has a strong understanding of low power design techniques, including UPF, clock gating, and power gating, which are vital for creating energy-efficient ASIC designs. His technical skills also encompass data path computation using Fixed Point Arithmetic (Q format) and knowledge of the Singular Value Decomposition (SVD) algorithm.