Hermione Chiew
About Hermione Chiew
Hermione Chiew is a Package Development Engineer at ON Semiconductor, where she has worked since 2013. She has contributed to various advancements in package development and process improvements in the semiconductor industry.
Work at ON Semiconductor
Hermione Chiew has been employed at ON Semiconductor since 2013, currently holding the position of Package Development Engineer. In this role, she has contributed to various projects and process improvements over her 11-year tenure in Negeri Sembilan, Malaysia. Prior to her current role, she worked as a High Income Talent Research Scientist Engineer (HIT-RSE) for nine months, starting in 2012, and also completed an industrial trainee program in 2010. Her experience at ON Semiconductor encompasses significant advancements in packaging technology and process optimization.
Education and Expertise
Hermione Chiew earned her Bachelor's Degree in Materials Engineering from Universiti of Malaya (UM), where she studied from 2008 to 2012. Her educational background includes a focus on materials science, which supports her expertise in package development and wafer processing. Prior to her university education, she completed her high school studies at Chan Wa Secondary School and SMK Tunku Ampuan Durah, where she pursued a science stream curriculum.
Background in Package Development
Hermione Chiew has a strong background in package development, particularly in the semiconductor industry. She has been involved in the development of various packages, including the X4DFN and X3DFN packages. Her work includes implementing process improvements to resolve issues such as WBC peeling and crack dies. She has also successfully developed wafer saw processes for different types of wafers, including alumina bumped wafers and Cu Power Metal wafers.
Technical Achievements
Throughout her career, Hermione Chiew has achieved several technical milestones. She pioneered the ability to saw the narrowest saw street of 20 um width and the smallest die size of 5x6 mils using a narrow dicing blade. She has successfully performed laser dicing on a 50 um saw street with a 4 mils thick WBC wafer and developed a 40 um saw street wafer with Au back metal. Additionally, she led a cost reduction project utilizing high-density lead frames and addressed tape residue issues during the final testing phase.
Process Improvement Initiatives
Hermione Chiew has actively contributed to process improvement initiatives within ON Semiconductor. She has implemented solutions to address various challenges, such as flying dies and tape residue issues. Her success in laminating CDAF tape on 2 mils thick wafers without breakage demonstrates her capability in enhancing manufacturing processes. Her involvement in GaN wafer dicing development projects further highlights her commitment to advancing semiconductor technology.