Jianan (Jeff) Yang
About Jianan (Jeff) Yang
Jianan (Jeff) Yang is a Senior Memory Compiler and Mixed Signal Design Engineer at ON Semiconductor, with extensive experience in memory architecture and high-speed interface design. He holds a Bachelor's degree in Physics from Peking University and a Ph.D. in Electrical Engineering from Purdue University.
Work at ON Semiconductor
Currently, Jianan (Jeff) Yang holds the position of Senior Memory Compiler and Mixed Signal Design Engineer at ON Semiconductor. He has been with the company since 2016, contributing to the development of memory architecture and circuit design. His role involves overseeing the architecture and circuit development of internal SRAM and ROM design/compiler, focusing on memory architecture innovation. Yang's work is critical in advancing the company's capabilities in mixed-signal design, particularly in the Austin, Texas area.
Previous Experience in Semiconductor Industry
Jianan (Jeff) Yang has extensive experience in the semiconductor industry. He worked at Motorola as a Semiconductor Device Engineer from 2001 to 2006, where he gained foundational knowledge in semiconductor technologies. Following this, he joined Freescale Semiconductor as a Circuit Design Engineer from 2006 to 2010, and then transitioned to NXP Semiconductors as a Memory Design Engineer from 2010 to 2016. His diverse roles have equipped him with a broad understanding of circuit and memory design.
Education and Expertise
Jianan (Jeff) Yang has a strong educational background in engineering and physics. He obtained his Bachelor's degree in Physics from Peking University, studying from 1990 to 1995. He then pursued further studies at Purdue University, earning a Master of Science in Electrical Engineering (MSEE) from 1995 to 1997, followed by a Doctor of Philosophy (Ph.D.) in Electrical Engineering from 1997 to 2001. His education has provided him with a solid foundation in both theoretical and practical aspects of electrical engineering.
Specialization in Memory Design and Low Power Techniques
Jianan (Jeff) Yang specializes in memory design and low power techniques. He is responsible for the architecture and circuit development of internal SRAM and ROM design/compiler, which highlights his focus on memory architecture innovation. Additionally, he has designed high-speed MIPI D-PHY/C-PHY for image sensor products, showcasing his expertise in high-speed interface design. Yang is also familiar with low power techniques such as power gating, write assist, and array biasing, indicating his commitment to power-efficient design strategies.