Jose Palagud
About Jose Palagud
Jose Palagud is a Wirebond Development Engineer with extensive experience in wirebond process engineering, having worked at notable companies such as On Semiconductor and Amkor Technology. He holds a Bachelor of Science in Electronics and Communications Engineering from Saint Louis University and has published works and patents related to multi-chip packages.
Current Role at On Semiconductor
Jose Palagud currently serves as a Wirebond Development Engineer at On Semiconductor Seremban. He has held this position since 2011, contributing to the development and optimization of wirebonding processes. His role involves conducting evaluations and characterizations of processes to enhance existing capabilities, as well as supporting new product introductions and engineering build requests.
Previous Experience in Wirebond Engineering
Prior to his current role, Jose Palagud worked as a Wirebond Process Engineer at On Semiconductor Seremban for 10 months in 2011. He also spent seven years at Amkor Technology Philippines in Sucat, Alabang, where he held the same position from 2004 to 2011. His earlier experience includes working as a Production Line Engineer and Maintenance Engineer at Nidec Precision Corp from 2001 to 2003.
Educational Background
Jose Palagud studied at Saint Louis University in the Philippines, where he earned a Bachelor of Science in Electronics and Communications Engineering. His studies spanned from 1996 to 2001, providing him with a solid foundation in electronics and communications principles.
Expertise in Wirebonding Technologies
Jose Palagud possesses expertise in various wirebonding technologies, specifically in Copper wire (Cu, CuPd, Pd doped Cu) and Silver (Ag Alloy) wirebonding. He is responsible for the qualification of new QFN devices and their derivatives, ensuring that the engineering builds meet the required specifications.
Publications and Patents
Jose Palagud has contributed to the field through published works, including 'MULTI-CHIP PACKAGES WITH STABILIZED DIE PADS' and 'QUAD FLAT NO LEADS PACKAGE.' He holds a patent for 'Multi-chip packages with stabilized die pads,' which reflects his innovative contributions to wirebonding technologies.