Kim Shuan Ooi
About Kim Shuan Ooi
Kim Shuan Ooi is a Principal Yield Enhancement Engineer at ON Semiconductor, with extensive experience in product engineering and yield enhancement across various companies in the semiconductor industry. He has a proven track record of improving product yield and data quality through innovative solutions and process enhancements.
Current Role at ON Semiconductor
Kim Shuan Ooi serves as a Principal Yield Enhancement Engineer at ON Semiconductor. He has held this position since 2019, contributing to various projects aimed at improving yield and efficiency in semiconductor manufacturing. His responsibilities include analyzing and enhancing yield performance across different production processes.
Previous Experience at NXP Semiconductors
Prior to his current role, Kim worked at NXP Semiconductors as a Principal Product Engineer (NPI) from 2018 to 2019 in Kaohsiung City, Taiwan. In this role, he focused on new product introduction, ensuring that new semiconductor products met quality and performance standards before market release.
Experience at Broadcom Inc.
Kim Shuan Ooi worked at Broadcom Inc. from 2014 to 2018 as a Test/Production Engineer Lead in Penang, Malaysia. During his tenure, he led teams in testing and production processes, contributing to the overall efficiency and quality of semiconductor products.
Educational Background in Electrical Engineering
Kim studied Electrical and Electronics Engineering at Universiti Putra Malaysia, where he earned a Bachelor of Electrical & Electronic Engineering from 2004 to 2008. His educational background provided him with a solid foundation in engineering principles, which he has applied throughout his career in the semiconductor industry.
Achievements in Yield Enhancement
Throughout his career, Kim has achieved significant improvements in yield and efficiency. He successfully deployed a big data analytic tool, Optimal Plus, in wafer sort and final test areas. Additionally, he enhanced the yield of high runner Analog Solution products from 95% to 99% and reduced wafer sort multisite yield loss from 10% to less than 5%.