Kok Kee Yang

Kok Kee Yang

Senior Manager Wafer Fab Process Engineering @ Onsemi

About Kok Kee Yang

Kok Kee Yang is a Senior Manager in Wafer Fab Process Engineering at onsemi, with extensive experience in process engineering and Six Sigma methodologies. He holds a Bachelor's Degree in Chemical Engineering from Universiti Teknologi Malaysia and a Master's Degree in Chemistry from the University of Malaya.

Current Role at Onsemi

Kok Kee Yang currently serves as the Senior Manager of Wafer Fab Process Engineering at onsemi. He has held this position since 2023, working on-site in Seremban, Negri Sembilan, Malaysia. In this role, he oversees the engineering processes involved in wafer fabrication, focusing on optimizing production efficiency and quality.

Previous Experience at Onsemi

Prior to his current role, Kok Kee Yang worked at onsemi as a Lean Six Sigma Manager from 2020 to 2023. During his three years in this position, he implemented process improvement strategies to enhance operational efficiency. He also served as a Certified Six Sigma Black Belt and Principal Engineer from 2013 to 2020, contributing to various engineering projects.

Career at NXP Semiconductors

Kok Kee Yang was employed at NXP Semiconductors from 2008 to 2013 as a Certified Six Sigma Black Belt and Staff Engineer specializing in End of Line processes. His five-year tenure involved managing quality control and process optimization initiatives within the semiconductor manufacturing environment.

Educational Background

Kok Kee Yang holds a Bachelor’s Degree in Chemical Engineering from Universiti Teknologi Malaysia, where he studied from 1999 to 2003. He furthered his education at the University of Malaya, earning a Master of Science in Chemistry from 2007 to 2010. His academic background provides a strong foundation for his engineering and management roles in the semiconductor industry.

Experience at Infineon Technologies

In 2013, Kok Kee Yang worked at Infineon Technologies as a Project Manager for New Device Introduction. His role lasted for six months and involved overseeing the introduction of new semiconductor devices, ensuring that projects met technical specifications and timelines.

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