Nirav Shah
About Nirav Shah
Nirav Shah is a Principal Engineer at ON Semiconductor with extensive experience in verification engineering and ASIC design. He has worked at eInfochips in various technical roles and has a solid educational background in Electronics & Communication from Hemchandracharya North Gujarat University.
Current Role at ON Semiconductor
Nirav Shah serves as a Principal Engineer at ON Semiconductor, a position he has held since 2019. He is based in San Jose, California, where he contributes to various engineering projects. His role involves leveraging his extensive background in verification and design engineering to enhance semiconductor technologies.
Previous Experience at eInfochips
Nirav Shah has a significant tenure at eInfochips (An Arrow Company), where he held various positions from 2006 to 2019. His roles included Verification Engineer, Member Technical Staff at different levels, and Sr Verification Engineer. He worked in locations such as Ahmedabad, Cedar Rapids, and San Jose, gaining diverse experience in verification and design.
Education and Technical Skills
Nirav Shah earned a Bachelor of Engineering degree in Electronics & Communication from Hemchandracharya North Gujarat University, completing his studies from 2000 to 2004. He possesses strong technical skills in industry-standard protocols, hardware verification languages, and EDA tools. His expertise includes protocols like PCIe, AXI, and DDR3, as well as proficiency in Verilog, SystemVerilog, and C++.
Industry Experience and Tools Proficiency
Nirav Shah has a comprehensive background in the semiconductor industry, having worked with various companies including Synopsys Inc, Globaltech, and ST-Ericsson. He is familiar with operating systems such as Linux and Windows, and version control tools like Cleartool and SVN. His hands-on experience extends to post-silicon validation of ASIC chips and lab validation.
Verification Architecture and Methodologies
Nirav Shah has extensive experience in defining verification architecture and developing scalable and reusable verification components. He possesses strong knowledge of UVM test flow and SystemVerilog randomization constraints, which are essential for effective hardware verification. His background enables him to contribute significantly to verification methodologies in semiconductor projects.