Sabbir Mazumder
About Sabbir Mazumder
Sabbir Mazumder is a Senior Layout Design Engineer with extensive experience in layout design and memory technologies, currently working at onsemi in Bengaluru, India. He has previously held positions at Micron Technology and Texas Instruments, specializing in CMOS and BiCMOS technology nodes, as well as DRAM technologies.
Work at Onsemi
Sabbir Mazumder currently serves as a Senior Layout Design Engineer at Onsemi, a position he has held since 2023. He works on-site in Bengaluru, Karnataka, India. In this role, he applies his extensive knowledge in layout design to contribute to the development of advanced semiconductor technologies.
Previous Experience at Micron Technology
Before joining Onsemi, Sabbir Mazumder worked at Micron Technology as an Engineer in DEG Layout from 2019 to 2023. During his four years in the Hyderabad Area, India, he focused on area estimation, floor planning of critical blocks, chip top routing, and verifications. His experience at Micron Technology enhanced his skills in the semiconductor industry.
Experience at Texas Instruments
Sabbir Mazumder was employed at Texas Instruments as an Analog Layout Engineer from 2017 to 2019. He worked in Bengaluru, Karnataka, India, for two years, where he gained significant experience in designing DRAM technologies, including LPDDR and GDDR5. This role contributed to his expertise in memory design.
Education and Expertise
Sabbir Mazumder holds a Bachelor of Engineering (B.E.) in Electronics and Telecommunication from Jorhat Institute of Science and Technology, where he studied from 2012 to 2016. He also earned a Diploma in Electronics and Telecommunication from Silchar Polytechnic, studying from 2009 to 2012. His educational background provides a strong foundation for his work in layout design and semiconductor technologies.
Technical Skills and Specializations
Sabbir Mazumder possesses a strong understanding of CMOS and BiCMOS technology nodes, with experience ranging from 180nm to 28nm. He is skilled in layout design tools such as Cadence Virtuoso/XL and Assura/Calibre. His expertise includes layout design, area estimation, and memory design, particularly in array structures.