Veenoshini Supparmaniam
About Veenoshini Supparmaniam
Veenoshini Supparmaniam is a Test Engineer II at ON Semiconductor in Seremban, Malaysia, with a background in Mechanical Engineering from Universiti Teknologi PETRONAS. She specializes in New Product Introduction and focuses on yield improvement and process enhancements.
Current Role as Test Engineer II
Currently, Veenoshini Supparmaniam holds the position of Test Engineer II at ON Semiconductor in Seremban, Negri Sembilan, Malaysia. She has been in this role since 2020, contributing to various projects and initiatives aimed at improving manufacturing processes. Her responsibilities include overseeing test programs and hardware on multiple platforms, ensuring that products meet quality standards.
Experience at ON Semiconductor
Veenoshini Supparmaniam has a significant history with ON Semiconductor. She completed an internship with the company in 2017, which lasted for 11 months in Malaysia. Following her internship, she worked as a Test Engineer from 2018 to 2020 for two years, where she gained valuable experience in the semiconductor industry before advancing to her current position.
Education and Expertise
Veenoshini Supparmaniam earned her Bachelor of Engineering (BE) in Mechanical Engineering from Universiti Teknologi PETRONAS, completing her studies from 2014 to 2018. Her educational background provides a strong foundation for her work in the semiconductor field, particularly in New Product Introduction (NPI), where she prepares test programs and hardware.
Specialization in New Product Introduction
Veenoshini specializes in New Product Introduction (NPI), focusing on preparing test programs and hardware on platforms such as Powertech, UIS, and Tesec RG. She conducts correlation studies between Monitor Probe and Final Test, identifying areas for improvement and collaborating with fabrication (FAB) teams to enhance device performance.
Focus on Yield Improvement and Process Enhancements
In her current role, Veenoshini Supparmaniam emphasizes yield improvement and scrap savings through process enhancements. She collaborates with FAB teams in monthly meetings to discuss wafer level improvements, aiming to optimize device performance and manufacturing efficiency.