Praveen P
About Praveen P
Praveen P is a Senior Software Engineer specializing in FPGA Design at QuEST Global in Bengaluru, India, with expertise in RTL design, Verilog, VHDL, verification, and FPGA implementation.
Company
Praveen P is currently employed at QuEST Global. He works as a Senior Software Engineer specializing in FPGA (Field Programmable Gate Array) Design. QuEST Global provides advanced engineering services to clients across multiple industries, and Praveen’s role is based in the Bengaluru Area, India. He started his tenure at QuEST Global on July 1, 2021.
Previous Roles
Prior to joining QuEST Global, Praveen P worked at Mistral Solutions Pvt. Ltd as an FPGA Design Engineer. His stint at Mistral Solutions lasted from 2019 to 2021, located in Bangalore Urban, Karnataka, India. Before Mistral Solutions, he served as a Design Verification Intern at SION Semiconductors Private Limited for 5 months between 2018 and 2019. Additionally, he was an Engineer Trainee at CDAC - Thiruvananthapuram for 11 months from 2014 to 2015.
Education and Expertise
Praveen P pursued his higher education at Govt. Engineering College, Barton Hill, Thiruvananthapuram where he studied Electronics with a focus on signal processing. He obtained his Master of Technology (MTech) degree from 2016 to 2018. His expertise includes RTL design, Verilog, VHDL, verification, and FPGA implementation. Praveen has hands-on experience in managing the complete project lifecycle, from requirement analysis to design, implementation, and testing.
Professional Experience in FPGA Design
Praveen P has accumulated 3 years of experience in FPGA design. His professional journey in this field includes comprehensive roles involving the full spectrum of FPGA design processes. This includes RTL design, using hardware description languages such as Verilog and VHDL, and verification tasks. He has been actively engaged in the implementation and testing phases of projects, ensuring the product meets the required specifications.