Avinash. U
About Avinash. U
Avinash U is a Senior Member of Technical Staff in Logic Design Engineering at Rambus, where he has worked since 2019. He holds a Master of Technology in Instrumentation and Applied Physics from the Indian Institute of Science and has extensive experience in low power design and debugging in high-speed digital circuits.
Current Role at Rambus
Avinash U currently holds the position of Senior Member of Technical Staff (SMTS) in Logic Design Engineering at Rambus, where he has been employed since 2019. His role involves significant responsibilities in the design and verification of complex logic systems. He has been instrumental in projects related to low power design and micro-architecture, particularly in the development of 32G PCIe GEN5 IP. His expertise includes handling timing closure activities and debugging issues related to testbench setups.
Previous Experience at Rambus
From 2016 to 2019, Avinash U worked at Rambus as a Member of Technical Staff (MTS) in Logic Design Engineering. During this period, he contributed to various projects in Bengaluru, India. His work included the development of half-rate Tap1 unrolled/speculative and direct feedback DFE architectures. He also managed SPYGLASS LINT and CDC checks for the entire Physical Medium Attachment (PMA), showcasing his proficiency in ensuring design integrity and compliance.
Educational Background
Avinash U has a solid educational foundation in engineering and applied physics. He earned a Master of Technology (M.Tech.) in Instrumentation and Applied Physics from the Indian Institute of Science, studying from 2014 to 2016. Prior to that, he completed a Bachelor of Engineering (B.E.) in Electronics and Communication Engineering at PES Institute of Technology from 2009 to 2013. His early education includes a Pre-University Certificate (PUC) from M.E.S PU College, where he studied PCMB from 2007 to 2009, and secondary education at SRI VANI PUBLIC SCHOOL, achieving I.C.S.E from 2004 to 2007.
Technical Expertise
Avinash U possesses extensive technical expertise in logic design and verification. He has micro-architecture level ownership of multiple blocks, including datapath, clocking, and RX adaptation of DFE and CTLE. His skills encompass front-end logical synthesis, flow setup, and logical equivalence checking (LEC). Additionally, he has developed and verified bring-up calibrations, such as PLL frequency calibration and voltage swing calibration, demonstrating his capability in complex design tasks.
Contributions to Design Projects
Avinash U has made significant contributions to various design projects throughout his career. He was involved in the low power design of 32G PCIe GEN5 IP, focusing on power intent micro-architecture and UPF development. His role also included debugging GLS issues, identifying testbench setup issues, and addressing X-propagation and glitch issues. He supported timing closure activities during the placement and CTS PNR stages in the 7nm node, highlighting his involvement in advanced semiconductor design processes.