Ehud (Udi) Nir ✪ I'm Hiring ✪
About Ehud (Udi) Nir ✪ I'm Hiring ✪
Ehud (Udi) Nir is the Director of Digital Engineering at Rambus, with extensive experience in ASIC design and engineering. He has held key positions at Huawei Technologies and IBM, contributing to numerous successful ASIC tapeouts and leading various engineering teams.
Current Role at Rambus
Ehud Nir serves as the Director of Digital Engineering at Rambus, a position he has held since 2021. In this role, he is responsible for overseeing digital engineering initiatives and managing teams focused on ASIC design and development. His leadership is critical in driving innovation and efficiency within the organization, particularly in the realm of digital engineering.
Previous Experience at Huawei Technologies
Prior to his current role, Nir worked at Huawei Technologies from 2012 to 2021, where he held multiple positions. He served as the ASIC/DSP design lead and group manager for high-speed interfaces in Ottawa, Ontario, from 2017 to 2021. During this time, he was responsible for numerous ASIC tapeouts in advanced nodes, achieving a tapeout rate of one every six months. Earlier, he was a VLSI group manager in Hod HaSharon, Israel, from 2012 to 2017.
Career at IBM
Ehud Nir's career includes significant experience at IBM, where he worked from 2005 to 2012. He began as a digital circuit designer and progressed to the role of SRAM Design team lead. His tenure at IBM involved leading design teams and contributing to various projects that enhanced the company's capabilities in digital circuit design.
Educational Background
Nir studied at Tel Aviv University, where he earned both his B.Sc. and M.Sc. degrees. He completed his B.Sc. in Electronic Engineering from 1997 to 2001 and his M.Sc. in Electrical and Electronics Engineering from 2009 to 2013. His education provided a strong foundation in engineering principles, which he has applied throughout his career.
Expertise in ASIC Design and Engineering
Ehud Nir possesses extensive expertise in ASIC design and engineering. He has hands-on experience with industry-leading EDA ecosystems and has overseen the entire ASIC design flow, including architecture, microarchitecture, power estimation, design, verification, backend, and signoff reviews. His technical skills are complemented by his leadership experience in managing engineering teams and projects.