Jinzhong Peng
About Jinzhong Peng
Jinzhong Peng is a Principal Engineer at Rambus, with extensive experience in analog circuit design and a strong background in semiconductor engineering. He has worked at various companies, including Rambus, Brite Semiconductor, and IDT, and holds multiple patents in the field.
Current Role at Rambus
Jinzhong Peng currently serves as a Principal Engineer at Rambus, a position he has held since 2022. His work is based in the United States. In this role, he applies his extensive knowledge in analog and mixed-signal integrated circuit design to develop innovative solutions in the semiconductor industry.
Previous Experience at Rambus
Prior to his current role, Jinzhong Peng worked at Rambus as Lead MTS Analog Engineering from 2016 to 2022. During his six years in the Raleigh-Durham, North Carolina area, he contributed to various projects and initiatives, enhancing the company's capabilities in analog engineering.
Education and Academic Achievements
Jinzhong Peng earned a Master of Science (MS) in Microelectronics from Shanghai Jiao Tong University, studying from 2006 to 2008. He also holds a Bachelor of Science (BS) in Telecommunications Engineering from Harbin University of Science and Technology, where he studied from 2000 to 2004. He received the Best Student Award at Shanghai Jiao Tong University in 2007.
Patents and Innovations
Jinzhong Peng holds a total of 14 patents, including 12 in China and 2 in the United States, primarily related to analog and mixed-signal IC design and phase-locked loop technology. His contributions to the field reflect his expertise and innovative approach to engineering challenges.
Technical Expertise and Skills
Jinzhong Peng has extensive experience in analog circuit design, particularly with SerDes circuits, including VGA, CTLE, DFE, Tx, and high-speed/low-jitter PLLs. He is knowledgeable in deep sub-micron process design, having worked with 55nm, 40nm, 28nm, and FinFET CMOS processes. His expertise also includes DDR5 RCD/DB, DDR4/3 RCD, and high-speed I/Os.