Jonghyun Cho

Jonghyun Cho

Pe Signal Integrity Engineer @ Rambus

About Jonghyun Cho

Jonghyun Cho is a PE Signal Integrity Engineer currently working at Rambus, where he specializes in DDR4/DDR5 buffer chip signal integrity. He has held various positions in academia and industry, including roles at Missouri University of Science and Technology and Korea Advanced Institute of Science and Technology.

Work at Rambus

Jonghyun Cho currently serves as a PE Signal Integrity Engineer at Rambus, a position he has held since 2020. Prior to this role, he worked as an SMTS II Signal Integrity Engineer from 2018 to 2020 and as an SMTS I Signal Integrity Engineer from 2017 to 2018. His responsibilities include conducting system-level Tx/Rx circuit evaluations, IBIS generation, and performing on-chip IR/EM/ESD checks. He also engages in package and board reviews, contributing to the design process starting from bump map decisions.

Education and Expertise

Jonghyun Cho holds a Doctor of Philosophy (PhD) in Electrical and Electronics Engineering from the Korea Advanced Institute of Science and Technology, which he completed from 2010 to 2013. He also earned a Master's degree in the same field from 2008 to 2010 and a Bachelor's degree from 2001 to 2008 at the same institution. His academic background provides a strong foundation for his expertise in signal integrity, particularly in DDR4/DDR5 buffer chip signal integrity work, system simulation, and various measurement techniques.

Background

Before joining Rambus, Jonghyun Cho worked at the Missouri University of Science and Technology as a Visiting Assistant Research Professor from 2015 to 2017. He also served as a Postdoctoral Researcher at the Korea Advanced Institute of Science and Technology from 2013 to 2014. His diverse experience in academia and industry has contributed to his comprehensive understanding of signal integrity and related engineering practices.

Technical Skills and Responsibilities

Jonghyun Cho specializes in signal integrity work related to DDR4 and DDR5 buffer chips. His technical responsibilities include system-level RMT measurement, VNA/scope measurement, and conducting various checks and evaluations. He is involved in the entire package design process, ensuring that all aspects of signal integrity are addressed from the initial design phase through to implementation.

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