Neethish Agari
About Neethish Agari
Neethish Agari is a Manager of Verification Engineering for Memory Interface Chips at Rambus, where he has worked since 2023. He has extensive experience in verification engineering, having previously held positions at Arm, Broadcom, and Sankalp Semiconductor, and possesses a strong background in formal verification and automated test equipment.
Current Role at Rambus
Neethish Agari currently serves as the Manager of Verification Engineering for the Memory Interface Chips Business Unit at Rambus. He has held this position since 2023, overseeing verification processes and leading engineering efforts in Bengaluru, Karnataka, India. His role involves managing a team and ensuring the successful execution of verification tasks related to memory interface chips.
Previous Experience at Arm
Before joining Rambus, Neethish worked at Arm as a Senior Engineer from 2018 to 2019 in Sweden. His experience at Arm contributed to his expertise in the semiconductor industry, particularly in the verification and design of integrated circuits.
Background in IC Design and Verification
Neethish has a solid background in integrated circuit design and verification. He worked at Broadcom as an IC Design Engineer from 2014 to 2016 in Bangalore. Additionally, he served as a Digital Verification Engineer at Sankalp Semiconductor Pvt Ltd from 2011 to 2014, where he developed verification environments and interfaces.
Educational Qualifications
Neethish Agari holds a Bachelor of Engineering in Electronics and Communications Engineering from N M A M Institute of Technology, NITTE, which he completed from 2006 to 2010. He further advanced his education by obtaining an Advanced Diploma in ASIC Design from RV VLSI Design Centre, Bangalore, studying VLSI Complete ASIC Flow from 2010 to 2011.
Technical Expertise and Tools
Neethish specializes in developing reusable parameterized UVC for various protocols and has a strong background in formal verification and co-simulation. He utilizes a range of tools for verification processes, including Cadence Xcelium, Vplanner, Vmanager, Stratus, Specman elite, Mentor Questasim, Mentor Visualizer, and Synopsys VCS. His work encompasses technologies such as DDR5, CXL, and various communication protocols.