Raghuraj S Bhat
About Raghuraj S Bhat
Raghuraj S Bhat is a Senior Member of Technical Staff at Rambus, specializing in verification processes and test bench development. He holds a Bachelor of Engineering in Electrical, Electronics and Communications Engineering and a Master of Technology in VLSI and Embedded Systems.
Work at Rambus
Raghuraj S Bhat currently holds the position of Senior Member Of Technical Staff at Rambus, where he has been employed since 2020. His role involves advanced verification processes, utilizing his expertise in constrained random verification and assertion-based verification techniques. He contributes to the development of test benches using SystemVerilog (SV) and Universal Verification Methodology (UVM). His work is integral to the verification of DDR5 Memory Interface IP, where he focuses on v-planning, defining tests and sequences, coverage, and assertions.
Education and Expertise
Raghuraj S Bhat earned a Bachelor of Engineering (B.E.) in Electrical, Electronics and Communications Engineering from Visvesvaraya Technological University, completing his studies from 2009 to 2013. He further advanced his education by obtaining a Master of Technology (MTech) in VLSI and Embedded Systems from Dayananda Sagar College of Engineering in Bangalore, from 2013 to 2015. His academic background supports his expertise in verification processes, particularly in constrained random verification and assertion-based verification techniques.
Previous Work Experience
Before joining Rambus, Raghuraj S Bhat worked in various engineering roles. He served as an Associate Staff Engineer at SAMSUNG R&D INSTITUTE INDIA - BANGALORE PRIVATE LIMITED from 2018 to 2020. Prior to that, he was a Design Verification Engineer at Aceic Design Technologies from 2015 to 2017. He also held the position of Project Engineer at Synapse Design Inc. for eight months in 2017. These roles provided him with a strong foundation in design verification and automation using Perl and Shell scripting.
Technical Skills
Raghuraj S Bhat possesses strong technical skills in verification methodologies. He specializes in developing test benches using SystemVerilog (SV) and Universal Verification Methodology (UVM). His expertise extends to constrained random verification and assertion-based verification techniques, which are crucial for ensuring the reliability and performance of electronic systems. He also utilizes Perl and Shell scripting for automation in verification processes, enhancing efficiency in his projects.