Sanjay Muchini
About Sanjay Muchini
Sanjay Muchini serves as the Senior Director of Engineering at Rambus, where he has worked since 2021. With extensive experience in engineering management and a strong background in SoC design, he has previously held leadership roles at Qualcomm, Texas Instruments, Intel, and Synopsys.
Current Role at Rambus
Sanjay Muchini serves as the Senior Director of Engineering at Rambus, a position he has held since 2021. In this role, he leads the Buffer Chip Engineering group, overseeing all functional teams involved in the development and delivery of chip designs. His responsibilities include managing engineering processes and ensuring the successful execution of projects within the organization.
Previous Experience at Qualcomm
Before joining Rambus, Sanjay Muchini worked at Qualcomm as Director of Engineering from 2008 to 2021. During his 13-year tenure in Bangalore, he contributed to various engineering initiatives and managed significant projects within the company. His experience at Qualcomm solidified his expertise in the semiconductor industry.
Engineering Background at Texas Instruments and Intel
Sanjay Muchini held the position of Engineering Manager at Texas Instruments from 2005 to 2007. He also worked at Intel Corporation as Manager of the PSV group for one year, from 2007 to 2008. These roles provided him with a strong foundation in engineering management and team leadership within the technology sector.
Education and Qualifications
Sanjay Muchini holds a Master of Science in Computer Engineering from the University of Louisiana at Lafayette. He also earned a Bachelor of Engineering in Electronics and Telecommunications from Osmania University. Additionally, he completed an MBA with a focus on Entrepreneurship and Finance at Santa Clara University. His educational background supports his technical and managerial capabilities in engineering.
Expertise in SoC Design and Engineering Management
Sanjay Muchini possesses a deep understanding of both front-end and back-end System on Chip (SoC) design processes. He is proficient in advanced computer architecture concepts and various Electronic Design Automation (EDA) tools for verification methodologies. His extensive experience includes managing large engineering teams, often leading groups of over 200 engineers, and delivering over 50 chip tape outs across technology nodes ranging from 65nm to 7nm.