Senthilkumaran K
About Senthilkumaran K
Senthilkumaran K is a SMTS Logic Verification Engineer with extensive experience in developing Verification IP for semiconductor products. He has worked at various companies, including Rambus and Synapse Design Inc., and holds a Bachelor's degree in Electrical and Electronics Engineering and a Master's degree in VLSI Design.
Current Role at Rambus
Currently, Senthilkumaran K serves as a Senior Member of Technical Staff (SMTS) Logic Verification Engineer at Rambus. He has held this position since 2019 in the Bengaluru Area, India. In this role, he focuses on ensuring the correctness of semiconductor designs through various verification methodologies.
Previous Experience in Semiconductor Verification
Senthilkumaran K has extensive experience in the semiconductor industry. He worked at Rambus as a Verification Consultant from 2017 to 2018. Prior to that, he held a position as a Verification Consultant at Analog Devices for five months in 2015. He also worked as a Project Engineer at Synapse Design Inc. for five months in 2017, and as an ASIC Verification Engineer at Aceic Design Technologies from 2015 to 2017.
Education and Expertise in Engineering
Senthilkumaran K holds a Bachelor's Degree in Electrical and Electronics Engineering from Tamilnadu College of Engineering, where he studied from 2009 to 2013. He furthered his education with a Master’s Degree in VLSI Design from Sona College of Technology, completing his studies from 2013 to 2015. His academic background supports his expertise in developing Verification IP for semiconductor products.
Technical Skills in Verification Methodologies
Senthilkumaran K possesses strong skills in various verification methodologies. He utilizes assertion-based verification methods to ensure design correctness and has hands-on experience with coverage-driven verification. Additionally, he is proficient in scripting with Perl, which aids in automating verification processes. His expertise also includes constraint random verification to enhance test coverage in ASIC design.